1. Technical Field
The present invention relates to a semiconductor device, and in particular to a semiconductor device which contains a complementary transistor having a stacked gate structure composed of a high-k gate insulating film and a metal gate electrode.
2. Background Art
Degradation in driving current due to depletion of polysilicon (poly-Si) electrode has been noticed as a growing problem, in development of complementary MOS (CMOS) device with the progress of shrinkage of constitutive transistors. Techniques for preventing degradation of the driving current has therefore been investigated, by adopting a metal gate electrode so as to avoid depletion of the electrode. Pure metal, metal nitride, silicides and so forth have been investigated as materials for composing the metal gate electrode. It is necessary for all cases that the threshold voltages (Vth) of both of N-type MOSFET and P-type MOSFET are adjustable to appropriate values.
For example, advanced CMOS transistors need Vth adjusted to ±0.1 V or around. It is therefore necessary to adopt a material having an effective work function (EWF) close to that of N-type polysilicon (4.0 eV) for the gate electrode of N-type MOSFET, and to adopt a material having EWF close to that of P-type polysilicon (5.2 eV) or around for the gate electrode of P-type MOSFET.
At present, titanium nitride (TiN) have widely been discussed as a candidate material for the metal gate electrode, from the viewpoints of its excellent thermal stability and readiness in patterning into gate electrode. TiN is, however, known to have EWF at around a mid-gap level of silicon over a high-k gate insulating film, so that it is impossible to achieve a necessary level of low Vth typically required for the N-type MOSFET, solely by this technique.
V. Narayanan et al. describe an N-type MOSFET having a SiO2 film, a high-k gate insulating film and a TiN electrode formed in this order over a substrate, and further having a lanthanum oxide film selectively introduced as a cap film between the high-k gate insulating film and the TiN electrode, so as to shift the flat-band voltage (VFB) towards the negative bias side, to thereby reduce EWF, and to consequently lower Vth (“Band-Edge High-Performance High-k/Metal Gate n-MOSFETs using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond”, 2006 Symposium on VLSI Technology Digest of Technical Papers, pp. 224-225).
The authors also describe that the shift of VFB towards the negative bias side increases as the thickness of the lanthanum oxide film increases, and thereby EWF may be lowered closed to the conduction band of Si, and a desired level of Vth may be obtained. In short, lanthanum functions as an adjusting metal capable of varying the threshold voltage of the N-type MOSFET.
Japanese Laid-Open Patent Publication No. 2006-108602 describes a semiconductor device having a p-well layer and an n-well layer formed in the surficial portion of a silicon substrate, and an n-channel MISFET and a p-channel MISFET respectively formed in the well layers while being partitioned by a device isolation region. The n-channel MISFET has a non-nitrogen-added n-channel interfacial layer; non-nitrogen-added n-channel high-k gate insulating film; and an n-channel gate electrode formed therein. Also n-type source/drain diffusion layers are provided. Whereas, the p-channel MISFET has a nitrogen-added p-channel interfacial layer; a nitrogen-added p-channel high-k gate insulating film; and a nitrogen-added p-channel gate electrode formed therein. Also p-type source/drain diffusion layers are provided.
According to the publication, thus-configured semiconductor device, having nitrogen contained in the gate insulating film composed of the high-k film and in the metal gate electrode, successfully forms a high-performance complementary MISFET having an improved hole mobility in the p-channel MISFET, without degrading electron mobility in the n-channel MISFET.
However, the present inventors have found the following problems. The technique proposed by V. Narayanan et al., making an effort of lowering Vth of the N-type MOSFET in the CMOS, by selectively introducing an adjusting metal such as lanthanum only into the N-type MOSFET, however, suffers from a problem as described below. In the CMOS, the adjusting metal such as lanthanum may selectively be formed only in the N-type MOSFET, by forming a lanthanum oxide film over the high-k gate insulating film of both the N-type MOSFET and the P-type MOSFET, then by forming a resist film which covers only the region having the N-type MOSFET formed therein, and by selectively removing the lanthanum oxide film in the P-type MOSFET. While the lanthanum oxide film herein might be removed typically by wet etching, also the high-k gate insulating film may adversely be affected by the etching solution in the process of removal of the lanthanum oxide film, enough to vary the thickness thereof. It is also anticipated that the lanthanum oxide film may partially remain in the P-type MOSFET. Since the above-described events may vary the thickness of the gate insulating film, so that Vth and gate inversion dielectric thickness (Tinv) of the transistor may vary, and thereby the CMOS may no longer achieve desired performances or may cause variation in the performances.